A manufacturing method of a semiconductor substrate is described in, for example, JP-A-2002-124474 (corresponding to US 2002/0158301) and JP-A-2006-19610. In the method, a trench is formed in the substrate, and an epitaxial film having high crystallinity is embedded in the trench. These two documents describe an object to provide the manufacturing method of the semiconductor substrate having a super junction (SJ) structure with PN columns. The substrate is suitably used for a semiconductor device having high break down voltage and low on-state resistance.
In the manufacturing method described in JP-A-2002-124474, a trench is formed in a silicon substrate. A mask made of an oxide film used in a trench process is removed. After that, a heat treatment is performed at temperature in a range between 900° C. and 1100° C. for a few minutes to tens minutes under reduced atmospheric pressure in non-oxidizing gas or non-azotizing gas. This heat treatment provides to smoothing an inner wall of the trench, which is roughened in the trench etching process. Then, the epitaxial film is embedded in the trench, so that the crystallinity of the epitaxial film is improved when the epitaxial film is grown in the trench.
In the manufacturing method described in JP-A-2006-19610, after a trench is formed in a silicon substrate, an inner wall of the trench is etched by a few nanometers to one micrometer with an etching gas including halogen gas such as HCl gas or Cl2 gas in a gas furnace chamber at around 1000° C. Thus, the inner wall of the trench is cleaned. Then, an epitaxial film is grown in the trench so that the trench is filled with the epitaxial film having high crystal quality without any void in the trench.
It is necessary to form a trench having a high aspect ratio in order to provide the PN columns in the SJ structure of the semiconductor substrate in JP-A-2002-124474 and JP-A-2006-19610, compared with a trench for forming a trench gate structure. When the trench having the high aspect ratio for the PN columns is formed, occurrence of crystal defects caused by an anisotropic etching process increases. In order to generate a depletion layer in the PN columns so that the device has the high break down voltage, it is important to restrict from inducing leak current. Since the PN columns do not include an insulation film, that is different from the trench gate structure, it is very important to restrict from generating crystal defects in the PN columns. Here, the crystal defects induce the leak current. However, it is not sufficient in the manufacturing method described in each of JP-A-2002-124474 and JP-A-2006-19610 to restrict the crystal defects when the aspect ratio of the trench for the PN columns is high. Thus, in the device in each of JP-A-2002-124474 and JP-A-2006-19610, it is not sufficient to remove a failure such as the leak current completely.